As feature sizes of CMOS devices continuously decrease in accordance with Moore Rule, development of CMOS integrated circuit encounters a great challenge. In order to overcome problems of small-size devices such as exponential increase of gate leakage current, severe polysilicon gate depletion, increasing gate resistance, and sever boron penetration of PMOS devices, it has become a consensus of the industry to use a high-K gate dielectric/metal gate structure to replace a conventional SiO2/polysilicon gate structure. However, there are still many problems to be solved to integrate the metal gate to the high-K gate dielectric. For example, thermal stability problem, interfacial state problem, and especially Fermi pinning effect place a great challenge in obtaining an appropriate low threshold voltage required by nanometer CMOS devices. It is especially the case for PMOS devices, because the high work function required by the PMOS devices is even difficult to obtain.